CS 221
Computer Organization and Assembly Language Programming

Spring 2023

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Software

See Quiz 4.

Readings

• Gates:
  • N2T: Chapter 1 (skip p. 25) (slides 3-4, 21-end)

• HDL examples:
  • Invite.hdl | Invite.cmp | Invite.tst
  • Mystery.hdl | Mystery.cmp | Mystery.tst

Description

This assignment will focus on creating digital circuits. The main tasks are:

• building and testing digital circuits in Logisim
• describing digital circuits in Hardware Description Language and testing the description in the Hardware Simulator

Build the circuits described in Project 1 (except Mux4Way16, Mux8Way16, DMux4Way, DMux8Way):

N2T: Project 1

Chapter 1 provides the contract for each circuit, i.e. description of its behavior, names and number inputs, names and state of outputs. The API is available here:

The Hack Chipset

Design in Logisim

Note the following additional requirements:

• arrange the circuits one after the other in the given order
• label the input pins as specified in the contract
• the topmost output pin of each circuit should include its given name and the name of the circuit:

  for example, for And16 the topmost pin will be named out_And16

• save the Logisim files in folder projects/01/

Here are additional specific requirements:

• Not, And, Or, Xor:
  • save in file named Basic.circ
  • only Nand, Not gates may be used; for Not only Nand

• Not16, And16, Or16:
  • save in file named Basic16.circ
  • only Nand, Not gates may be used; for Not only Nand

• Or8Way:
  • save in file named Or8Way.circ
  • uses 1 input pin of width 8 that is split immediately into 8 wires of width 1 (use Splitter under Wiring)
  • only basic gates allowed
  • minimize circuit depth, i.e. #levels to right; (hint: merge sort)

• Mux/Mux16:
  • save in file named Mux.circ
  • only basic/basic16 gates allowed
  • for the select input use Bit Extender

• DMux/DMux16:
  • save in file named DMux.circ
  • only basic/basic16 gates allowed
  • the select input will need to be widened (use Bit Extender under Wiring)

• Mux4Way16, Mux8Way16, DMux4Way, DMux8Way: not required

Design in HDL

Note the following additional requirements:

• Not, And, Or, Xor: only Nand, Not gates may be used; for Not only Nand

• Not16, And16, Or16:
  • only Nand16, Not16 gates may be used; for Not16 only Nand16
  • Nand16 is not built-in, so download and complete the following file:

    Nand16.hdl

  • create your own Nand16.tst, Nand16.cmp; model after And16.(tst|cmp)

• Or8Way:
  • note that in the contract the input is 1 pin of width 8
  • only basic gates allowed
  • minimize circuit depth, i.e. #levels to right; (hint: merge sort)

• Mux, DMux: only basic gates allowed

• Extender16: download the following file and complete the code for the chip:

  Extender16.hdl (needed to widen selector for Mux16 and DMux16)

• Mux16, DMux16:
  • only basic16 gates allowed and Extender16
  • create your own DMux16.hdl, DMux16.tst, DMux16.cmp; model after Mux16
  • from main menu: View→View→Output (shows output of your circuit); View→View→Compare (shows expected result);

• Mux4Way16, Mux8Way16, DMux4Way, DMux8Way: not required

Modify and test the respective .hdl file given by the authors in folder projects/01/:

• Win users: could use Notepad (shows line numbers at bottom right)
• Mac users: could use TextEdit; ensure file is edited and saved in Plain Text: "Format Menu:Make Plain Text"

What to turn in

Zip folder 01/ in file named 01.zip and upload it to the Moodle dropbox.