Readings
- ALU:
- N2T: Section 2.2.2, 2.3 (p39), 2.4, 2.5 (slides 44-58, 65)
- Bits, Registers, Counters:
- N2T: Section 3 Intro, 3.1 (ignore Memories/RAM), 3.2.1, 3.2.2, 3.2.4, 3.3 (ignore Memories/RAM), 3.4, 3.5 (slides 1-6, 11-23, 32-35, 47-49, 53, 54, 59, 60-64)
Description
This assignment will focus on the following tasks:
- building the major computing device, the ALU
- build simple memory components
Build the
ALU circuit described in Project 2 and the
Bit and
Register circuits described in Project 3:
N2T: Project 2
N2T: Project 3
Chapters 2 and 3 provide the contract for each circuit, i.e. description of its behavior, names and number inputs, names and state of outputs.
Design in Logisim
Note the following requirements:
- create empty folder
cs221/03/ and save the Logisim files there
- arrange the circuits one after the other in the given order
- label the input pins as specified in the contract
- the topmost output pin of each circuit should include its given name and the name of the circuit:
for example, for And16 the topmost pin will be named out_And16
Here are additional specific requirements:
Splitter: Logisim has a component called Splitter under Wiring; it can be used to select a single bit from a bus (or a group of bits)
Constants: note that Constants components can be given width which makes it possible to propagate multiple 1s or 0s on a wide bus
ALU:
- save in file named ALU.circ
- recall that Multiplexers have "if" meaning
- use the Logisim versions of previously built-components (e.g.
Adder)
- you may convert a single
Or component into Or16Way
- minimal use of basic gates
- note on testing:
- initially do not include the (status) outputs
zr, and ng
- after the
ALU can perform the operations in Table 2.6, add the (status) outputs
- submit screenshots that show evidence of testing based on the following configurations in Table 2.6:
- case1.png: control pins set as in row for
-x with inputs x=1011,y=1001
- case2.png: control pins set as in row for
y+1 with inputs x=1110,y=FFFF
- case3.png: control pins set as in row for
x-y with inputs x=1010,y=1101
- each image size no larger than 500KB
Bit:
- save in file named Bit.circ
Bit should be built primarily of D Flip-Flop under Memory- do not change the
D Flip-Flop properties and only use the D, Q, and clock pins
- for testing you will need to attach a clock
- minimal use of basic gates
Register:
- save in file named Register.circ
- for the Logisim version the main input and output will be of width 8, i.e. the circuit will only store 8-bit numbers
Register is just a parallel sequence Bit components- for the
Bit component use a 1-bit version of Register under
- for testing will need to attach a clock
- minimal use of basic gates
Design in HDL
Note the following additional requirements:
- in folder cs221/03/ copy one at a time the starter code for the required circuits:
Bit.(hdl|ts|cmp)Register.(hdl|tst|cmp)
Here are additional specific requirements:
Splitter:
- to achieve the effect of splitting wires in HDL you write
gatepin=wire[i..j] or gatepin[i..j]=wire (the widths have to match)
more generally, you can write gatepin[i..j]=wire[p..q] (the widths have to match), but this general version will not be needed for this assignment
gatepin could be an input or output pin of the gate
Constants:
- to achieve the effect of sending the constant values 1 or 0 to a pin in HDL you write
gatepin=true or gatepin=false (should work regardless of pin width)
Or16Way:
- create
Or16Way chip saved in Or16Way.hdl; as simple as possible with as few gates as possible; reuse similar existing chips from previous assignments
- create your own Or16Way.hdl, Or16Way.tst, Or16Way.cmp; model after the existing similar version (it is fine to just copy each data value twice to match the width)
ALU:
- recall that Multiplexers have
"if" meaning
- use the chips built in previous assignments (e.g. Adder)
- minimal use of basic gates
- note on testing:
- initially ignore the (status) outputs
zr, and ng; simply do not mention them anywhere in ALU.hdl
- for testing use the provided files ALU-nostat.tst and ALU-nostat.cmp (no status)
- later add the (status) outputs and for testing use the provided files ALU.tst and ALU.cmp (complete)
Bit:
Bit should be built primarily of the built-in DFF chip- minimal use of basic gates
Register:
Register is just a parallel sequence Bit chips- minimal use of basic gates
Modify and test the respective .hdl file given by the authors:
- Win users: could use Notepad (shows line numbers at bottom right)
- Mac users: could use TextEdit; ensure file is edited and saved in Plain Text: "Format Menu:Make Plain Text"
