CS 221
Computer Organization and Assembly Language Programming

Spring 2023

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Readings

• CPU:
  • N2T: Chapter 5 Intro, 5.1.4, 5.2.1, 5.2.2, 5.3.1, (slides 27-48, 78-81)
  • N2T: Chapter 4 Intro, 4.1.2, 4.2.1, 4.2.2, 4.2.3, (slides 7-16, 19-23, 33-37, 41-47)

Description

This assignment will focus on the following tasks:

• building the CPU

Build the CPU circuit described in Project 5:

N2T: Project 5

Chapter 5 provides the contract for each circuit, i.e. description of its behavior, names and number inputs, names and state of outputs. The API is available here:

The Hack Chipset

Design in Logisim

Note the following requirements:

• create empty folder cs221/06/ and save the Logisim files there
• label the input pins exactly as specified in the contract:
  • if there are multiple circuits in the same file, add pin index, i.e. a1, a2, a3
  • if a name is rejected, add _pin, i.e. in_pin, out_pin

Here are additional specific requirements:

• For this project we will us a different version of Logisim:

  Download Logisim 4.0.4hc

  Your circuits, ALU, PC, Jumper, have been made compatible with the new version of Logisim:

  you can download the compatible circuits from the Assignment 9 dropbox on Moodle as a .zip file.

  No corrections have been made to the circuits, if they did not work correctly originally.

• Loader [not in the book, combinational gate]:

  Chip name: Loader
  Inputs:    d1, d2, d3,    // same meaning as Figure 4.4, p.68
             ctype          // 1 if instruction is ctype
  Outputs:   loadA, loadD, loadM   // set to 1 if inputs indicate value should be loaded
                                   // any subset of these may be 1
  

  This is similar to the Jumper and allows us to decide whether A, D, or M should load a new value.

  Create a circuit that with the following inputs and outputs:

  • save in Loader.circ
  • 1-bit inputs  d1, d2, d3 : same meaning as in Figure 4.5, p.69
  • 1-bit input  ctype : why is it needed?
  • 1-bit outputs  loadA, loadD, loadM : indicate which component needs to load a value (all or some could be 1)
  • moderate use of basic gates

• CPU Setup (1):
  • start new Logisim project and save in file named CPU.circ; then create four additional subcircuits in this project as follows:
    • do this separately for each circuit: ALU, Jumper, PC
    • from Menu Bar: "Project=>Add Circuit..."
    • use "Open..." or cut and paste the circuit

    This will allow you to drag your own circuits as boxed components onto the CPU Canvas. It essentially creates a small library similar to Wiring, Arithmetic, etc:

• CPU Setup (2) - this step is optional:
  • save the following file in folder cs221/06/:

    nand2tetris.jar

  • from Menu Bar: "Project=>Load Library=>Jar Library..."
  • find the file that you downloaded: nand2tetris.jar
  • in dialog box type: edu.gburg.nand2tetris.Components
  • should see a new library at the bottom called nand2tetris

• CPU:
  • follow the diagram in Figure 5.8 on page 20
  • you could consider immediately splitting the instruction into its 16 bits
  • for testing you will need to attach a clock
  • minimal use of basic gates

• CPU Testing - short test session is available here:

  CPU Testing

• Splitter: Logisim has a component called Splitter under Wiring; it can be used to select a single bit from a bus (or a group of bits)

• Constants: note that Constants components can be given width which makes it possible to propagate multiple 1s or 0s on a wide bus

Design in HDL

Note the following additional requirements:

• in folder cs221/06/ copy one at a time the starter code for the required circuits:
  • CPU.(hdl|tst|cmp)
  • Jumper.hdl

Here are additional specific requirements:

• Loader:
  • see description above
  • save in Loader.hdl
  • moderate use of basic gates

• Test Loader:
  • download test files: Loader.tst | Loader.cmp (fill in missing values)
  • test in Hardware Simulator
  • in the submission include Loader.cmp

• CPU:
  • save in file named CPU.hdl and follow the diagram in Figure 5.8 on page 20
  • use ARegister and DRegister which are specialized versions for the plain Register
  • minimal use of basic gates

• Splitter: to achieve the effect of splitting wires in HDL you write gatepin=wire[i..j] or gatepin[i..j]=wire (the widths have to match)

  more generally, you can write gatepin[i..j]=wire[p..q] (the widths have to match), but this general version will not be needed for this assignment

  gatepin could be an input or output pin of the gate

• Constants: to achieve the effect of sending the constant values 1 or 0 to a pin in HDL you write gatepin=true or gatepin=false (should work regardless of pin width)

Modify and test the respective .hdl file given by the authors:

• Win users: could use Notepad (shows line numbers at bottom right)
• Mac users: could use TextEdit; ensure file is edited and saved in Plain Text: "Format Menu:Make Plain Text"

What to turn in

Zip folder 06/ in file named 06.zip and upload it to the Moodle dropbox.